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DRESPA: An Integrated System for Reconfigurable High-speed Signal Processing Applications


Ramadass Narayanadass, Natarajan Somasundaram, J. Raja Paul Perinbam


Vol. 7  No. 8  pp. 1-7


This paper describes DRESPA (Dynamically Reconfigurable Embedded Signal Processing Architecture) developed for the class of real-time high-speed signal processing applications. DRESPA is a coarse-grained, multi-programmable and dynamically reconfigurable architecture. The architecture consists of arithmetic operation-level configurable modules interconnected through multiple data buses that can be logically configured to form one or more computation pipelines before a specific application is initiated, and remains unchanged till the completion of the application. On-chip integration of reconfigurable logic reduces the memory access cost and the reconfiguration cost. It neither requires an external processor to configure it, nor does it consume context change-over time. The suitability of DRESPA for the target application domain is evaluated with real-time signal processing applications such as video processing, image processing and speech processing. The results show that there is a performance improvement in terms of speedup in comparison with other systems.


Reconfigurable Computing, Embedded System, Digital Signal Processing, High Speed Architecture