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A Novel Architecture and Mechanism for High-Performance Real-Time Intrusion Detection and Response System


Jintae Oh, Byoungkoo Kim, Seungyong Yoon, Jong-Soo Jang, Yong-Hee Jeon, Jaecheol Ryou


Vol. 8  No. 3  pp. 155-162


Many Network Intrusion Detection System(NIDS)s have been developed to detect and respond against several kinds of intrusion activities in widespread networks. Due to the explosive growth of network bandwidth, software approach in developing a high-speed NIDS is becoming impractical due to the performance constraint. Accordingly, it seems unavoidable to investigate the hardware-based solutions. Another critical problem of NIDS is a problem of false positive alerts. In order to solve these two problems, we propose a high-performance real-time intrusion detection and response system that has FPGA-based reconfiguring hardware architecture and SPI(Stateful Packet Inspection)-based intrusion detection module in the FPGA. In this paper, we present the novel architecture and mechanisms for design and implementing the system. Some experimental results are also provided.


Intrusion detection, header lookup, SPI(Stateful Packet Inspection), pattern matching