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Audio Power Amplifier Solutions for New Wireless Phones


Salahddine Krit, Hassan Qjidaa


Vol. 9  No. 1  pp. 155-159


This paper presents a single chip class D amplifier with two selectable gains 6dB & 9dB, 1.4 W output power and 86% efficiency with an 8 ohm load. This chip uses a frequencies trim-able ramp generator. Input Clock Frequency Range with 250kHz ? 550kHz and 8 bits trim, 4 bits (LSB) to trim the ramp amplitude to vdd/5 peak-to-peak, 4 bits (MSB) to adjust the ramp continuity, the trimming procedures consists on putting a zero input signal, and adjust the trim code such as to get a 50% duty cycle Pulse Wide Modulation output signal, Reduction of inter-modulation in case of mixing of Audio and Voice. It operates with a 2.5 V to 5.5V supply voltage, 0.5 um, double-poly, triple-metal BiCMOS process. It has an area of 1.5 x 1.2 mm2 and it achieves a THD as low as 0.04%, with a flatband response between 20 Hz and 20 kHz.


single chip class D, selectable gains, trim-able ramp, output power, efficiency