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Impact of Faulty Links on Quality-of-Service in Network-on-Chip under Different Traffic Patterns


Krishan Kumar Paliwal, Vijay Janyani, M.S.Gaur, Vijay Laxmi


Vol. 9  No. 3  pp. 108-117


The objective of this paper is to introduce the impact of faulty links on Quality of Service in Network-on-Chip (NoC) under different traffic pattern. NoC paradigm has made it possible to concurrently run multiple applications on IP-core based System on Chip. It is therefore necessary to predict the multi-processor systems-on-chip communication, which is a critical issue and needs to be addressed by the right mix of soft and hard real-time guarantees. To meet this requirement state of the art packet switched NoC provide different levels of quality of service (QoS) such as best effort (BE) and guaranteed throughput (GT). This paper presents a novel scheme which compares and evaluates the performance of guaranteed throughput and best effort traffic in Network-on-Chip under different synthetic traffic generators and highlights its dependence in terms of latency on the type of traffic patterns and number of link failures for mesh topology. It also explores the effect of robustness of a particular traffic pattern in terms of fault tolerance (variation in average latency as the number of link failures increases) for planar adapter routing function on latency of GT and BE traffic class for mesh topology.


Guaranteed Throughput, Best Effort, robustness, fault tolerance and QoS