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System-on-Chip Test-time and Scan-power Minimization Integrating Core and Interconnect Testing


Gautam Das, Santanu Chattopadhyay, Haripada Bhaumik


Vol. 9  No. 3  pp. 201-209


This paper presents a Genetic Algorithm (GA) based strategy to solve the problem of System-on-Chip testing. It addresses the issues like core and interconnect testing, while most of the previous works reported in the literature takes care of core testing alone. The scheduling results produced show the trade-off between the testing time and power dissipated s while shifting the test patterns and responses through scan chains. This provides a wide range of choice for the designer to select a suitable test architecture.


SoC testing, Core, Interconnect test, Scan-power, Power optimization