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Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers


Muhammad H. Rais, Syed M. Qasim


Vol. 10  No. 1  pp. 69-74


A high performance substitution box (S-Box) implementation using reduced residue of prime numbers is presented in this paper. The byte substitution implemented using S-Box is an important part of the Advanced Encryption Standard (AES). The objective of this paper is to present an efficient Field Programmable Gate Array (FPGA) realization of S-Box using very high speed integrated circuit hardware description language (VHDL). The design was implemented on Xilinx Virtex-5 XC5VLX50 FPGA and the results obtained show that the proposed method provides an improved performance with 38% improvement in maximum clock frequency as well as efficient utilization of FPGA hardware resources.


Advanced Encryption Standard (AES), S-Box, FPGA, VHDL, Virtex-5