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Virtex-5 FPGA Based Braun’s Multipliers


Muhammad H. Rais, Mohammed H. Al Mijalli


Vol. 11  No. 8  pp. 81-84


Fast Fourier transform (FFT) and Finite Impulse Response (FIR) are examples of digital signal processing (DSP) applications, which require high execution speed. Parallel array multipliers implementation on field programmable gate arrays (FPGAs) can fulfill high execution speed. The Virtex-5 FPGA resource utilization is obtained for 4×4, 6×6, 8×8 and 12×12 bit Braun’s multipliers. The analysis of variance (ANOVA) and post hoc Tukey’s test using the Statistical Package for Social Science (SPSS) are applied to find out significant difference using delay time effect in 4×4, 6×6, 8×8 and 12×12 bit Braun’s multipliers. The ANOVA and Tukey HSD multiple comparison with .05 confidence level suggests that all of the 4×4, 6×6, 8×8 and 12×12 bit Braun’s multipliers implemented on Virtex-5 are significant to each other. The statistics of mean delay time with standard deviation and mean error is also presented.


Brauns multipliers, Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), Virtex-5, VHDL