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Title |
An On-Chip Delay Measurement Technique for Small-Delay Defect Detection Using Signature Registers |
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Author |
RAJESHWARI SOMA, ZULEKHA TABASSUM, S.PRATHAP |
| Citation |
Vol. 14 No. 9 pp. 60-66 |
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Abstract |
This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18- m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that oftest set for normal testing on average. |
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Keywords |
Delay estimation, design for testability (DFT), integrated circuit measurements, semiconductor device reliability, signature register |
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