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A Retargetable Compiler for Cell-Array-Based Self-Reconfigurable Architecture


Masayuki Hiromoto, Shin’ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura


Vol. 7  No. 4  pp. 131-139


Simulation-based quantitative performance evaluation using specific applications is indispensable for developing architectures of self-reconfigurable devices since static analysis is difficult to estimate their performance. In order to generate configuration data needed for simulating various target architectures, we developed a synthesis tool which can be retargeted to various self-reconfigurable devices specified by architecture parameters. Given an application in C-language, our tool automatically executes data-flow analysis, technology mapping, and layout synthesis. Our tool enables us to perform efficient design-space exploration, and its retargetability helps fair evaluation of the devices on the same platform. This paper also shows architecture evaluation examples using our tool to demonstrate the advantage of our tool.


coarse-grain, ALU-based reconfigurable architecture, high-level synthesis, layout synthesis