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Title

Using Dead Block Information to Minimize I-cache Leakage Energy

Author

Mohan G Kabadi, Ranjani Parthasarathi

Citation

Vol. 7  No. 5  pp. 95-105

Abstract

Power-conscious design using hardware and/or software means has become crucial for both mobile and high performance processors. This paper explores integrated software and circuit level technique to reduce the leakage energy in iL1-cache of high performance microprocessors by eliminating the basic blocks from the cache, soon after they become ‘dead’. The impact of eliminating dead blocks on processor performance and energy efficiency are analyzed in detail. The compiler normally identifies the basic blocks from the control flow graph of the program. At this stage candidate basic blocks that can be turned-off after use are identified. This information is conveyed to the processor, by annotating the first instruction of the selected basic blocks. During execution, the basic blocks are kept track of, and after use, the cache blocks occupied by these blocks are switched-off. Experiments have been conducted by considering two different initial states of the cache - on and off, and the leakage energy saved varies from 0.09% to a maximum of 96.664%.

Keywords

Power-efficient architecture, Low-leakage cache, Compiler-assisted energy optimization

URL

http://paper.ijcsns.org/07_book/200705/20070515.pdf