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Implementation of Novel Pipeline VLIW Architecture in FPGA


R.Seshasayanan, Dr S.K.Srivatsa


Vol. 7  No. 7  pp. 264-268


Technology has seen the development of processor industry right from micro to the latest Nano-technology with Speed and performance being important criteria, not much attention has been given to the power requirement for these integrated Circuits. Present fully synchronous processors have evolved with a Global clock which is supplied throughout the die; this has resulted in unwanted power consumption and dissipation. The other significant problem is supply of this global clock with a low skew through the entire die. Each and every existing synchronous processor cannot be converted to Asynchronous processors due to certain design constraints such as complexity and compatibility. An architecture, which is a hybrid between a fully synchronous and an Asynchronous processor, termed as Globally Asynchronous and Locally Synchronous processor (GALS) is being incorporated in our design. We propose to analyze a Very Long Instruction Word (VLIW) processor which exploits Instruction Level Parallelism (ILP) to increase the speed of execution. Simulation analysis is done on a prototype VLIW processor under GALS multiprocessor environment to reduce power with same performance.


Globally Asynchronous Locally Synchronous (GALS), Very Long Instruction Word (VLIW), Field programmable gate array (FPGA) etc