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Design and Performance analysis of efficient bus arbitration schemes for on-chip shared bus Multi-processor SoC


Neeta Doifode, Dinesh Padole, P.R. Bajaj


Vol. 8  No. 9  pp. 250-255


In the resource sharing mechanism of multi-processor SoC, the on-chip communication architecture plays an important role and directly affects the performance of SoC. The traditional shared bus arbitration schemes show the several defects such as bus starvation, and low system performance. In this paper, we discuss about the static & dynamic Lottery Bus algorithms. ATM switch architecture is also discussed which is based on a probability and uses an adaptive ticket value method to solve the problem of Lottery Bus arbitration schemes. The discussed architectures are modeled using VHDL, and simulated in ModelSim software. The comparison of these three arbitration schemes with respect of performance parameters such as average latency, acceptance rate & bandwidth waiting time are presented. The simulation results shows the ATM switch architecture decrease the bus request latency by 49%


System-on-Chip (SoC), Bus Arbiter, VHDL, Multiprocessor