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Hardware Implementation of The Chameleon Polymorphic Cipher-192


Magdy Saeb


Vol. 9  No. 11  pp. 240-249


The Chameleon Cipher-192 is a polymorphic cipher that uses a variable word size and variable-size user’s key. The cipher employs a shuffler and two nonlinearity-associated filters for selective addition. The cipher structure is based on the simultaneous use of block and stream cipher approaches. Other elements of the cipher include a specially-developed hash function for key expansion. In addition, this hash acts as a PRG to provide a random input to the filters. These filters are designed to elaborate the enciphering sequence by irregularly interrupting the data encryption at pseudo random, however, recoverable intervals. The cipher provides concepts of key-dependent number of rotations, key-dependent number of rounds and key-dependent addresses of substitution tables. The parameters used to generate the different substitution words are likewise key-dependent. In a previous work, we have established that the self-modifying proposed cipher, based on the aforementioned key-dependencies, provides an algorithm polymorphism and adequate security with a simple parallelizable structure. In this work, we provide an analysis of this cipher and an FPGA implementation.


FPGA, Cipher, Polymorphic, Hardware, Analysis