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New Experimental Results for AES-CCMP Acceleration on Cyclone-II FPGA


Chakib Alaoui


Vol. 10  No. 4  pp. 1-6


This paper presents a possible solution for accelerating IEEE 802.11i. First, it offloads the process of AES-CCMP encryption from the master CPU onto a co-processor, which frees the master CPU resources for other uses. Second, its implementation on FPGA offers the possibility of using many threads to run the AES-CCMP encryption. Different optimizations have been applied on the hardware architecture of AES and on the basic unit of AES-CCMP, in order to satisfy different constraints in terms of latency, area occupation and speed. Performance measurement of the hardware solution is compared to AES software implemented on a NIOS II processor. A strong focus is devoted to the achievement of high throughput, which is required to support security requirements for current and future high bandwidth applications.


IEEE 802.11i, AES-CCMP, Cipher, WEP, FPGA Input