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Implementation of FPGA based Firewall Using Behavioral Synthesis


Rajanish K. Kamat, Pawan K. Gaikwad, Santosh A. Shinde


Vol. 10  No. 6  pp. 199-203


Behavioral design helps the designer to understand the design space and subsequently coming up with a design that meets all the constraints specifically in a field programmable gate array (FPGA) based design paradigm. In this paper we have reported a novel design framework for creation of behavioral design. We have examined the opportunities brought about by finite state machines and to harness them into a synthesizable register transfer level (RTL) architecture. We discuss a case study of packet parser its finite state machine (FSM), data path controller architecture and issues related to its Handel-C implementation.


Firewall, FPGA, Handel C, Behavioral Synthesis, ASIC