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FPGA Based Fixed Width 4×4, 6×6, 8×8 and 12×12-Bit Multipliers using Spartan-3AN


Muhammad H. Rais, Mohamed H. Al Mijalli


Vol. 11  No. 2  pp. 61-68


In this study we investigate the Field Programmable Gate Array (FPGA) implementation of fixed width 4×4, 6×6, 8×8, and 12×12 standard and truncated multipliers using Very High speed integrated circuit Hardware Description Language. Multiplier is a core operation for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT). The implementation of DSP algorithm requires Application Specific Integrated Circuits (ASICs). The image processing applications requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with ASICs because they are not reconfigurable and cost is very high. The FPGA is a viable technology that could be implemented and reconfigured at the same time, since FPGA have the benefit of hardware speed and the flexibility of software. In this study we achieved remarkable reduction in FPGA resources, power and delay when the full precision of standard multiplier is not required and the truncated multiplier can be implemented with fewer resources, power and delay. The comparisons of FPGA layout show that the standard multipliers utilize lot of space as compared to truncated multipliers which could be utilized for other embedded resources.


Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), Spartan-3AN, Truncated Multiplier VHDL