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Delay Study of Virtex-2, Virtex-4 and Spartan-3E Based Truncated Multipliers


Mohammed H. Al Mijalli


Vol. 11  No. 7  pp. 68-71


Medical imaging technology requires real time efficient algorithms. The aim of this paper is to present the Field Programmable Gate Array (FPGA) based truncated multipliers delay study, implemented on Spartan-3E, Virtex-2 and Virtex-4 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using analysis of variance (ANOVA) method using the software Statistical Package for Social Science (SPSS). The one way ANOVA method followed by post hoc Tukey’s test using the software SPSS with a .05 significance level was used to compare the FPGA devices. Multiple comparison tests revealed that the differences between the FPGA devices are significant with a 95% confidence level. In all three FPGA devices as the size of truncated multipliers increases their mean latency value is also increases.


Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), Spartan-3E, Truncated Multiplier, Virtex-2, Virtex-4, VHDL.