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Implementing FFT Algorithms on FPGA


Arman Chahardahcherik, Yousef S. Kavian, Otto Strobel, Ridha Rejeb


Vol. 11  No. 11  pp. 148-156


The hardware description and modeling of digital signal processing (DSP) algorithms and applications for implementing on Field Programmable Gate Array (FPGA) chips are challenging issues. In this paper, some practical Fast Fourier Transform (FFT) algorithms including Cooley-Tukey, Good-Thomas, Radix-2 and Rader methods are modeled by Verilog hardware description language and their performance are compared in terms of chip area utilization and maximum frequency operation. The results of synthesizing FFT algorithms by ISE tool on XC3S5000 chip, from XILINX Inc. demonstrate that the Radix-2 FFT method uses the least number of Slices and the Cooley-Tukey and Good-Thomas approaches use the most number of Slices. In term of Flip-Flop utilization, the Cooley-Tukey and Good-Thomas approaches use less than the Radix-2 and Rader approaches. Furthermore, for all methods, the utilized FPGA chip area increases by increasing the number of FFT points. The Radix-2 is the fastest method for calculating FFT. The Good-Thomas method is faster than Cooley-Tukey where there are no coefficients between DFT blocks and the Rader method has the worst operating frequency on FPGA between all proposed FFT approaches.


FFT Algorithms, Cooley-Tukey, Good-Thomas, Radix-2, Rader, FPGA, Verilog