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A Pseudo 12-bits 8,33MS/s Charge Redistribution Successive-Approximation ADC in CMOS 65nm for Image Sensors


Malika Alami Marktani, Ali Ahaitouf, Abdelaziz Ahaitouf, Stephane Vivien


Vol. 12  No. 4  pp. 19-28


A new charge redistribution Successive Approximation A-D Converter (SA ADC) potentially suitable for array implementation in CMOS Imagers is presented. The performances achieved exceed the performances of the actual sensors in terms of both resolution and image quality. The reached sampling rate is more than sufficient for mobile applications (30fps for a pixel array of 5Megapixels). The converter is designed in CMOS 65nm technology and the low power constraints have been respected, the consumed silicon area was optimized in order to fit into the actual sensors die size with no major changes affecting the other blocks, thus this new conversion system will be readily usable in image sensors of next generation with pitches less than or equal to 1.1?m.


CMOS Image Sensors, column-level ADC, Successive Approximations ADC, Differential Charge Redistribution DAC, Fringe capacitor